The present application relates to sensor signals from pixel sensors of an image sensor. More particularly, the present application relates to aggregating signals from active pixel sensors of an image sensor to achieve different readout resolutions without excessive aliasing artifacts.
An image sensor typically includes an array of pixel sensors arranged in an array. In some instances, it is desirable to xe2x80x9cbinxe2x80x9d the outputs of such a pixel sensor to accomplish a reduced-resolution image with better image quality than is achievable by simply subsampling.
One known application of binning includes generating a reduced resolution video image or viewfinder xe2x80x9cpreviewxe2x80x9d image from an imager that is capable of producing a high-resolution still image. Another binning application includes operating, in a super-high-speed low-resolution mode, an imager that is capable of producing a standard or high-resolution video output.
There are a number of ways to achieve binning. For example, with an image sensor that has charge-coupled device (CCD) pixel sensors, binning is typically achieved by clocking the charges produced by the individual CCD pixel sensors into a summing well. The summed charge is then typically converted to a voltage for further processing. For CCD imagers, a well-known benefit to binning is the improvement of the signal-to-noise ratio. See, for example, U.S. Pat. No. 5,773,832 to Sayed et al.
Recently, there has been a trend towards using Complementary Metal Oxide Semiconductor (CMOS) imagers. CMOS imagers have an advantage that they can be read out more flexibly than CCD imagers. Furthermore, CMOS imagers can be made with standard silicon processes in high-volume foundries. As a result, as improvements are made in semiconductor processes and material technology, CMOS imagers can benefit from those improvements.
Direct binning of the outputs of CMOS imager pixel sensors has been limited to collecting charges from the photodiodes of passive pixel sensors and directly mixing the charges; see, for example, U.S. Pat. No. 5,970,115 to Colbeth et al, and U.S. Pat. No. 5,262,871 to Wilder et al.
Binning of outputs from active pixel sensors has been limited to special binning circuits added onto column lines, to mix signals across columns, and across sequential row reads, by charge sharing. See, for example, U.S. Pat. No. 5,949,483 to Fossum et al. Another binning approach utilized with CMOS imagers having active pixel sensors is described in U.S. Pat. Nos. 5,909,026 and 6,057,539 to Zhou et al. The Zhou patents disclose storing into a frame memory array data corresponding to signals output from an active pixel sensor array. That is, each active pixel sensor in an active pixel sensor array has a corresponding memory cell in the frame memory array. Each memory cell includes a capacitor into which the output signal from the corresponding active pixel sensor is sampled. A memory row decoder and column select (for example, operating under the control of a resolution control circuit) control the resolution of the image data read out from the frame memory array. With the conventional active-pixel-sensor binning approaches just described, each row is read separately, so there is no speed advantage over non-binning approaches.
What is desired is a simple and flexible approach to combining the outputs of active pixel sensors of an image sensor.
In accordance with an aspect of the invention, an active pixel sensor imager is configured to aggregate the follower-type amplifier outputs of subgroups of the active pixel sensors by controlling the imager to couple together the follower-type amplifier outputs of those active pixel sensors to an output node for each column. Row select signal generating circuitry is employed to accomplish the selection. Column select signal generating circuitry is employed to accomplish aggregation of the signals at the column output nodes to an imager output node. Advantages are that pixel noise is reduced, the frame readout time is reduced, and image aliasing is reduced.